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SIMPIO: SIMPIO & Combo logic design
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Step One : Learning to Use the website interface

 

  1. Objective: Nibble reversal of the input given by the user using SIMPIO application.

 

  1. Details: This programs the FPGA with a bitfile, which is stored in server which inturn takes in a hexadecimal input   and nibble reverses it to produce the output.

 

             Sample input: 87ae                      Sample output: ea78

 

Step Two :

 

  1. Objective: The user should able to generate the bit file for the nibble reversal program, upload the bit file and enter the same input as used in Step ONE to the check the result. 

 

  1. Details: This step is to make sure that the user is comfortable with the design flow. The bit file here is again for nibble reversal like STEP ONE but bit file is generated and uploaded from the user end.

 

Step Three :

 

  1. Objective: Learn to modify the vhdl template to implement incrementor.

 

  1. Details: The VHDL template (template_simpio.vhd) has provided for modification at indicated areas to implement combinational circuits with two inputs and one output by the student. With the modified template_simpio.vhd and the files in the Template folder are synthesized and generated bit file has to be uploaded by the student.
     

Step Four :

 

  1. Objective: The user has to modify the template to implement multiple input multiple output combinational circuits.

 

  1. Details: The VHDL template (template_simpio.vhd) has provided for modification at indicated areas to implement combinational circuits with multiple inputs and multiple output by the student. With the modified template_simpio.vhd and the files in the Template folder are synthesized and generated bit file has to be uploaded by the student. 

 


                           

 

 

           

 

Cite this Simulator:

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