An FSM is a digital sequential circuit which can go through a sequence of states as controlled by the designer. The state refers to one of the stable operating modes of the circuit represented in terms of the output of "next state" logic part of the FSM. The control is as defined by the designer of FSM and if the clock is present in the control then its a synchronous FSM which we will entertain in this design. So FSM is a circuit which can jump through different states and produce different outputs at different states as is defined by the designer. If the output of current state depends on any of the inputs to the FSM along with the current state then it is called a Mealy FSM. If the output depends on only the state of FSM then it is a Moore machine. However they are equivalent, as you will see in your classes.
To summarize, FSM has a output logic + next state logic + memory(state register) to store the state. In this experiment we designs Mealy FSM.
Fig 1. Mealy FSM [source: http://electrosofts.com/verilog/mealy.gif]
Fig 2. Moore FSM [source: http://electrosofts.com/verilog/fsm.gif]