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FSM: FSM Design
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STEP ONE: FSM DEMO

 

  1. Objective: To show simple FSM implementation with reset signal.

 

  1. Details: In this experiment user is asked for entering an input along with the reset. Upon receiving the inputs, a simple FSM which is already configured onto the FPGA will be trigerred to change state. The new state and output can be seen in the new webpage. The user can check the following FSM by giving corresponding inputs

 

 

                                      Si: states available for transition, where i = 1,2,3,4

                                 A/B : A is 2 bit input, B is 3 bit output

                                   rst : reset signal = '1'

                            Others : All possible input sequences for which state transitions from the current state is not  shown.


STEP TWO:  User-defined FSM - single input to single input port

 

  1. Objective: Implement FSM by modifing template file
  2. Details: The user can download the template vhdl files for designing their own fsm from the link provided. The template file shows the code for the above fsm. The user is expected to modify the code to tune it to their requirements. The user can submit one input and observe the result of the same (single stepping mode).

 

 STEP THREE: User-defined FSM - sequence of inputs to single input port

 

  1. Objective: Implement generic FSM by modifing template file
  2. Details:  The user can have multiple outputs in his/her vhdl design description. The format of how to go around  this is specified in the template vhdl files which can be downloaded from the specified link. However user can have only one input of size <= 32bits. Rather than giving the input one by one user is supposed to upload the text file containing the sequence of inputs for which the fsm needs to be exercised. The template format of the input file can also be downloaded. Remember the input provided should be written in the decimal format rather than in binary.

 

 STEP FOUR: User-defined FSM - sequence of inputs to multiple input port

 

  1. Objective:  Implement FSM multiple inputs and multiple outputs
  2. Details: Here the user can define multiple input multiple output fsm, with a constraint of the size of the inputs (sum of the bit widths of all the input lines) should not exceed 32 bits.

 

 

Example: For example say we have 3 inputs in our design, each of 8 bit width. So the total width = 8 + 8 + 8 =  24 which is less than 32. So this is a realizable design. The user need not specify the number of inputs anywhere in the website. Rather he should follow the template format for giving the inputs, which can be downloaded from the website. Here the inputs are taken as binary numbers and different inputs are separated by using commas (,) in between them (see the input file template). The user should take care of the repercussions of these conventions in the vhdl design description. The user can look into the template vhdl files (which can be downloaded from the website) to see how this is taken care of, for the implemented fsm shown below.


 

 

 FSM has two inputs and two outputs. Input 1 – 1bit, Input 2 – 2 bit. Output 1 – 2bit, Output 2 – 1 bit


                           Si: states available for transition, where i = 1,2,3,4

                A|B/C|D: A is 1 bit input1, B is 2 bit input2, C is 2 bit output1, D is 1 bit output2

                         rst: reset signal = '1'

                  Others: All possible input sequences for which state transitions from the current state is not

 

 

 

 

 

 

 

Cite this Simulator:

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