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MEMDTI: Memory data transfer & Interface
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 STEP ONE: Demos-Guide the user to access the memory available in the ADMXRC board

  1. Objective_1: Accessing single bank from memory (ZBT SRAM).

  2. Details:This demo shows how one of the 6 banks of memory (ZBT SRAM), present in the ADMXRC board is accessed (read and write). This demo reads the 32 bit data from all locations of bank number five(available banks are bank0 - bank5) one by one, exor it with "FFFFFFFF" and writes back the result to the same location of the same bank from which it is read from. The initial and final contents of the bank5 can be seen in the result window.

 

  1. Objective_2: Accessing mutiple banks from memory (ZBT SRAM).

  2. Details: This demo shows how all the six banks available can be accessed(read and write). This demo reads the data from bank 0,2 and 4 and write them respectively into locations of the bank 1,3,5.

  

  1. Objective_3: Accessing Contiguous locations from memory (ZBT SRAM).

  2. Details: This demo shows how the user can pipeline the accesses to memory. To give more clarity to the user, this experiment essentially demonstrates the following.

    1. User can write or read from different banks simultaneously, since each bank has independent control,data and address bus.
    2. User can give contiguous address location reads in consecutive clock cycles. The first data will be valid in the data bus after 5 clock cycles, from the issue of first address. Consecutive data will be available thereafter in consecutive cycles. i.e;
      Issue reads to addresses A,A+1,A+2,A+3... of bank B at clocks C,C+1,C+2,C+3... The data will be valid at C+5,C+6,C+7,C+8..., where data at C+5 corresponds to address A of bank B.
      For contiguous writes no waiting(as in case of reading) is required. Send the data D1,D2,D3... to addresses A,A+1,A+2.. of bank B at clocks C,C+1,C+2... respectively.

 

STEP TWO: Bank-0 access

  1. Objective: To enable user to implement the application which needs an external memory of 1 MB. However the user is allowed to use only bank0 of available 6 banks.

  2. Procedure: The user should download the template files and make necessary changes in user_module which suits their application. Upload the synthesized bit file. Then upload the necessary input file in the format specified along with the other details asked for. The user is advised to read the comments provide in the user_module.vhd to get the overall idea of how the hardware functions.

STEP THREE: Single memory bank access

  1. Objective: To enable user to implement the application which needs an external memory of 1 MB. The user is allowed to use any bank of available 6 banks.

  2. Procedure: The user should download the template files and make necessary changes in user_module which suits their application. Upload the synthesized bit file. Then upload the necessary input file in the format specified along with the other details asked for (like which bank you need to access, starting location of accesses, ending location of accesses ). The user is advised to read the comments provide in the user_module.vhd to get the overall idea of how the hardware functions.

 

STEP FOUR: Multiple memory bank access

  1. Objective :  To enable user to implement the application which uses 2 banks of available 6 banks.

  2. Procedure: An example design is provided in the template provided which does the following.

for addresses 0 to 50 do

Reads value from location 'address' of bank-2.

Adds decimal 10 value to the read value.

Write back the processed value to bank-3 location 'address+5'.

 

User can change the banks (here 2 and 3 are used). However remember to change the port names in the entity declaration of user_module.vhd and similarly portmap those properly in the top_module.vhd. Follow the instructions given in the previous STEP.

 

STEP FIVE:

  1. Objective: To enable user to perform any application which can make use of all the banks.

  2. Procedure: The user is asked to provide their own C-file(respecting the template C-file format) and the bit file required to download onto the FPGA.

    1. The user should provide the number of input files other than mentioned above which you need to get uploaded onto the server are used in your design.
    2. The user should also provide the number of output files which he needs to download. Essentially this is the result of the processing done on the FPGA.
      • For example: if you need to do an image filtering application using FPGA, you would probably upload an image file and a filter function file and gets a filtered output image file. So here the number of input files = 2 and output files = 1.
    3. The user will be navigated to next web page if no errors are encountered while loading the bit file and c file. Remember the extension of the bit file should be .bit and c file should be .c file.
    4. Now user should upload the input files which his design needs.
    5. The user program will be executed and the result will be displayed in the next web page.

 

 

 

Note: Please go through the reading material to get more information on writing the file =><=

 

 

Cite this Simulator:

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